Christian Schuler's Forward Error Correction (FEC) Page

This site contains some examples of Forward Error Correction (FEC) software and hardware, which has been developed at GMD-FOKUS, a research institute in Berlin, Germany. Since 2000 the institute changed it's name to FHG-FOKUS.

You will find software and hardware examples for free download, which are available as 'C' source code or binaries (tested under Linux and Solaris), VHDL source code or as 'VHDL' code generators for SUN/Solaris. VHDL (Very High Speed Hardware Description Language) is a highly specialized programming language used in ASIC design.

The programs have been developed in several research projects on wireless communication systems and may be used for academic or personal purposes. They haven't been optimized nor will any warranty be given on correct implementation or operation. The main interest was the engineering or implementation point of view, so for those more mathematically interested it might not be very useful.

I want to thank Ascan Morlang, who is the author of the genenc tool.

Very helpful for the FEC implementation were the examples from Robert Morelos-Zaragoza and Phil Karn, to which I want to express my thanks at this place.

Also I want to thank my Ph.D. supervisor Prof. Dr.-Ing. habil Prof. e.h. Dr. h.c. Radu Popescu-Zeletin at FHG-FOKUS.

FEC Software

fec_perf - three 'C' programs for performance estimation of BCH, RS and selected convolutional codes.

rs_decode - software RS encoder/decoder in 'C', features:

- fully parameterized: code parameters (n,k,m) can be selected via command line options

- decoding optional by Euclid or Belekam-Massey algorithm

- support of shortened codes

- extensive 'verbose' levels for hardware verification

- bch_matrix - calculates the G and H matrix from an arbitrary BCH generator polynomial

Hardware and Code Generators:

The following examples are VHDL code generators written in 'C'. The user enters the desired code parameters and the program produces synthesizable VHDL code for the codec. In addition a behavioral VHDL testbench can be nerated. The VHDL code has been simulated with the Model Technology Simulator V5.1c, and has been synthesized with Exemplar Logic Leonardo V4.2 for various XILINX FPGA architectures. In a real application it will be necessary to optimize the design for the specific requirements, but it may be a good starting point.

VHDL source code examples:

CRC32 encoder - generated with the genenc code generation tool.

RS(32,28) encoder - generated with the genenc code generation tool.

RS(32,28) decoder - generated with the genrs code generation tool.

VHDL code generators:

genenc - VHDL code generator for CRC, BCH and RS encoder (binaries for Sun/Solaris, HPUX, Linux 2.0)

- written by Ascan Morlang

- polynomials can be entered via command line

- variable bus width

- automatic testbench generation

venomgen - source code version of genenc

gen_gf - package with VHDL code generators for various Galois field arithmetic functions (C source code for Sun/Solaris)

- constant multiplier

- general multiplier

- power function (used in division circuit)

genrs - VHDL code generator for a generic RS decoder (source code and binaries for Sun/Solaris), features:

- fully parameterized: m,n and k can be entered via command line options

- synthesizable VHDL code (RTL level)

- automatic generation of a VHDL testbench for simulation
use of on chip RAM components (needs synchronous internal RAMs as available in XILINX XC4000E,EX,XL series !)

pcc - encoding and decoding (Viterbi) software for punctured convolutional codes (PCC)

- pcc_dec - Viterbi software decoder for punctured convolutional codes

- ccencgen - convolutional code VHDL encoder generator

- vitgen - Viterbi decoder VHDL generator

I provide all software examples in one compressed package. Please note that there is no Windows version, all software is Unix command line based.

Related Information

The Error Correcting Codes Home Page


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Christian Schuler

Updated 02 Nov 2015